Order Code: LAP-16032U
- 16 logic analyser channels.
- Sampling rates up to 100MHz.
- 64Kbits per channel memory depth (through the use of compression this can be increased to a maximum of 16Mbits).
- I2C, SPI, UART and 7-segment display protocol decoding as standard.
- Two free protocol decoding options of your choice from those listed below. After ordering, just telephone or email us with your choices.
- Extensive range of further protocol decoding options available. Allow for your two free protocol decoding options and then order any that are also required, either with your logic analyser or at a later date.
- Powered from PC’s USB port.
- Lightweight, compact and extremely portable.
- Supplied with USB cable, test leads and sprung-loaded test clips.
Not long ago a logic analyser represented a considerable investment for most electronics companies and their cost put them beyond the reach of hobbyists. Even with the advent of PC-based logic analysers, they could still cost upwards of several hundred pounds. Now all this changes with this high-quality 16-channel 100MHz logic analyser priced at under £100.
The LAP-16032U is an incredibly easy to set up and use 16-channel logic analyser. Extremely compact and lightweight, the LAP-16032U connects to and is powered by the USB port of any desktop or laptop PC making it very portable and ideal for use in the field. The LAP-16032U provides sampling rates up to 100MHz and 32Kbits memory depth per channel. Furthermore Zeroplus’s patented compression techniques allow up to 8Mbits memory depth per channel. Additional features include I2C, SPI, UART and 7-segment display protocol decoding and output connections allowing synchronisation with other test equipment such as.
Internal clock (timing mode): 100Hz – 100MHz
External clock (state mode): 100MHz
Working range: -6 ~ +6V
Maximum input voltage: ±30V
Total memory: 1Mbits
Depth per channel: 32Kbits (up to 8Mbits with compression)
Trigger channel: 16 channels
Pre/post trigger: yes
Trigger level: 1 level
Trigger count: 1 ~ 65535
Time base range: 5ps ~ 10Ms
Vertical sizing: 1 ~ 5.5
Enable delay: yes
Data compression: 16Mbits maximum
Width display: yes
Maximum trigger page: 128 ~ 8192 pages
Trigger delay: yes
Infinite increase spacer bar: yes
Automatic zoom in of spacer bar: yes
Automatic software upgrade: yes
Data range selectable: yes
Bus inquiry and counter: yes
Enable bar: yes
Bus analyser module plug-in: yes
Bus package list: yes
Power: from USB
Power at rest: 1W
Power at work: 2W
Enhance your LAP-16032U by adding additional protocol decoding options. Any of those listed below can be bought separately to complement the I2C, SPI, UART and 7-segment display decoding features provided as standard. These comprise software and upgrade codes and so may be ordered whenever required and not just when ordering a logic analyser. Don’t forget that you can request any two of these free of charge with your LAP-16032U.